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Job Description:
Develops and supports design for test (DFT) structures. Determines design for
test approaches and develops DFT architecture. Designs and verifies DFT
structures for memories (MBIST), digital and analog circuitry. Performs scan
synthesis. Creates, simulates and verifies automatic generated test patterns
(ATPG). Creates functional tests and corresponding test patterns. Knows about
failure mechanisms in silicon production and creates test algorithms. Supports
silicon bring up of test patterns. Performs diagnosis of test patterns on
silicon and optimizes test time.
Qualifications:
- You must possess the minimum qualifications to be initially considered for
this position.
- Preferred qualifications are in addition to the minimum requirements and are
considered a plus factor in identifying top candidates.
- Relevant experience can be obtained through schoolwork, classes and project
work, internships, and/or work experience.
- Minimum Qualifications 10 years of experience with RTL (Verilog, System
Verilog, VHDL), Synthesis (using Design Compiler), Static Timing Analysis
(using Prime Time), Simulation
- Bachelor's Degree in Electrical Engineering, Computer Engineering or related
field Synopsys Design Constraints for synthesis and timing signoff.
- Experience in Design Verification (DV) using standard simulators e.g. VCS,
QuestaSim, NCSim.
- Experience in Post Silicon Bring Up Support and interfacing customer.
- Experience in managing cross function groups and external customers.
- Experience with IP (DDR5/4/3, PCIe, Ethernet, ...) integration is a plus.
- Experience with host interconnects (Amba, Avalon, ...) is a plus.